In digital systems, flip-flops are important components, having impact on all aspects of the performance of the digital systems, such as area, power consumption and speed, etc. In the design of the modern Very Large Scale Integration (VLSI), how to increase the speed of the chip, lower the power consumption, and save the area of the silicon wafer has become more and more important. As the important components of the digital system, how to improve the design of the flip-flops and how to design flip-flops with low power consumption and high speed are the major tasks to enhance the performance of the entire system. The conventional master-slave flip-flops have certain characteristics, such as relative complex circuit structures and the positive setup time, etc. Thus, it is difficult for the conventional master-slave flip-flops to achieve relative high speeds. D flip-flops are commonly used flip-flops. Among the D flip-flops, the double edge D flip-flops are widely used because of their relatively strong anti-interference ability.
The mainstream structure of the existing double-edge D flip-flops includes parallel-connected single-edge master-slave flip-flops. Such a flip-flop structure includes two parts: a clock raising-edge triggered D flip-flop and a clock falling-edge triggered flip-flop. The flip-flops having such a structure have a relative large power consumption; and the setup time is positive.
Another existing type of flip-flops are the pulse double-edge D flip-flops. A pulse double-edge D flip-flop includes a pulse signal generating circuit and a latching circuit; and responds to the raising-edge and the falling-edge of a clock signal. The pulse signal generating circuit generates narrow pulse signals; and the latching circuit samples the input signals of the D flip-flop. Two coupled inverters at the output terminals of the latching circuit latch the output signals of the D flip-flop. The setup time of the D flip-flops having such a structure is negative, more suitable to be applied in high-speed circuits. However, such D flip-flops are easy to generate redundant narrow signals; and the redundant narrow signals increase the power consumption of the circuit.
Thus, the power consumption of the existing D flip-flops is still relatively high. The disclosed circuit structures and methods are directed to solve the above mentioned issues and other problems in the art.